Digital band-pass filter for a single circuit full duplex transmission system

ABSTRACT

A full duplex data communications system using a single transmission circuit is shown. Each terminal of the system has its receiver circuit provided with a digital filter to remove from its input circuit, the frequencies being used for data transmission at that terminal. The digital filter is switchable by the data signal to be transmitted and will be set to block from the receiver, the particular frequencies then being used to transmit data. In the preferred embodiment, the signal on the transmission line is converted to a delta modulated signal which is combined with its prior signal delayed by an interval dependent upon the data being transmitted from that terminal to generate a delta modulated filtered signal carrying the received data. The filtered signal is then converted to recover the received data.

United States Patent 1191 Jones, Jr.

[ 1 Feb. 6, 1973 [54] DIGITAL BAND-PASS FILTER FOR A 3,566,031 2/1971Carbone ..17s/59 SINGLE CIRCUIT FULL DUPLEX TRANSMISSION SYSTEM 1Primary Examiner-Ralph D. Blakeslee 1. v, V 1 n AssistantExaminer-Thomas DAmico 7 F PEF- 991 1912-4999#:15919 5113219...Alwrny-D9W9y1Cunningham n n. [73] Assignee: International BusinessMachines U V V V Corporation, Armonk, N.Y. [57] ABSTRACT [22] Filed:1971 A full duplex data communications system using a sin- [211 App].191,295 gle transmission circuit is shown. Each terminal of the systemhas its receiver circuit provided with a digital filter to remove fromits input circuit, the frequencies U.S. 178/58, R, being used for datatransmission at terminal The 325/30, 325/320 digital filter isswitchable by the data signal to be Int. Cl- .1104] transmitted and beset to block from the receiver 3] Field of Search 5 the particularfrequencies then being used to transmit 333/70 70 70 data. In thepreferred embodiment, the signal on the 179/2 2 343/175 transmissionline is converted to a delta modulated signal which is combined with itsprior signal delayed Referellwi Clled by an interval dependent upon thedata being transmitted from that terminal to generate a delta modu-UNITED STATES PATENTS. lated filtered signal carrying the received data.The fil- 3,s77,202 1971 Brightman ..178/58 R e ed signal is thenconverted to recover the received 3,655,915 4/1972 Libennan ..l78/58 Rdata. 3,651,433 3/1972 Langley ..330/70 T 1 3,543,172 11/1970 Seppeler..307/233 4 Claims. 5 Draw/Ins Flames 3,649,759 3/1972 Buzzard ..l79/2DP FSK 24 51 ,amsumen 57 I 52 COUNTER RESET NOR ,45

55 ........L.. F 111 mm I38 59 51 jg; L l 40 NOR I if I 42 45 i3 14 m I$5 1/ I 1 L FF I OSCILLATORI 52 V V V HIGHEST as as 25 1 01105111111 A0R F To 7 4 911* DIGITAL I ur FSK DATA a1 1 85 ii DOWN o1 SCRIM- 2 14 Icounter 1 NATOR I n A J SH'FT 15 511117 31 REGISTER PAILNIHJFEU 6 I8733,715,496

sum 10F 2 FIG. 1 H PRIOR ART w W FSK TRANSMIT w TRANSMITTER DATACOMMUNICATION Q FREQUENCY RECEIVED DISCRIMINATOR 0m RECEIVED 21 22 DATASIGNAL INPUT 26\ FIG. 2 S|GNAL I DELAY f(f)+f('t-T) 25 SIGNAL FREOUENCYfFSK TRANSMIT TRANSMITTER DATA 2e 22 14 FREQ RECEIVED I DELAYDISCRIMINATOR DATA couuumcmou ELEMENT INVENTOR GARDNER D. JONES, JR.

ATTORN EY DIGITAL BAND-PASS FILTER FOR A SINGLE CIRCUIT FULL DUPLEXTRANSMISSION SYSTEM OBJECTS OF THE INVENTION A data transmission using asingle communications circuit to transmit data in a full duplex modebetween two terminals is already well known and is in public use. Thesystem 'uses two different frequency bands, one for each direction oftransmission and provides each receiver with a band-pass filter to allowonly the signals emanating from the other terminal to be processed. Suchfilters are large and expensive since they require tuned circuits in theaudio frequency range and are additionally not completely effective. Therequirement of passing a band of frequencies or conversely of blockingsuch a band received from the local transmitter will prevent the use ofa very sharp filter and therefore will allow some of the unwantedfrequencies to pass into the receiver. Such undesired signals can causedistortion and may introduce data errors.

It is therefore an object of this invention to provide a full duplexcommunications system using only a single transmission circuit andincluding an improved transmitter-receiver isolation filter.

It is another object of the invention to provide in such acommunications system an isolation filter which is selectively settableto the frequency being transmitted from a station to thereby remove itseffect on the receiver at the station.

It is a further object to provide an isolation filter which isautomatically settable by the data to be transmitted from a terminal toblock application to a receiver of the signal frequencies transmittingthe data.

Still another object is to disclose a digitally operating transmissionsystem which requires no large and expensive frequency responsivecomponents to isolate a receiver from the signals being transmitted froman ad jacent transmitter.

A still further object is to devise a filter having a very sharpattenuation characteristic at its fundamental frequency and at oddharmonics thereof and constructed of digital type, on-off circuits only.

Another object is the provision of a delta modulated filter connected inthe input circuit of a receiver to neutralize the effect on saidreceiver of a strong signal applied to the input of said receiver.

All of these and other objects, features and advantages will be apparentin the following description of a preferred embodiment of the inventionas shown in the accompanying drawings.

DESCRIPTION OF THE DRAWINGS I delay filter for full duplextransmissions; and

FIG. 4 is a detailed schematic showing of a digital implementation ofthe filter and transmitter implementation.

OPERATION OF THE SYSTEM One known type of transmission system,identified as the 103 type, enables the use of a single pair oftelephone type wires for full duplex data communications. The signalsare transmitted in one direction using one frequency band and aretransmitted in the other direction using a different frequency band. Ateach end of the line, the frequency band used for transmissions fromthat end is filtered out of the total signal on the line leaving onlythe signal received from the other end of the line. As indicated in FIG.1, digital data to be transmitted is received on a line 10 and controlsa frequency shift keying (FSK) transmitter 11 to supply to an outputline 12, two distinct frequency signals in a narrow frequency band, e.g.1070 Hz for a zero data bit and 1270 Hz for a one data bit. Thesesignals are passed through a junction 13 to a communications line Datawill also be received from the communications line 14 at the junction 13in a different frequency band, e.g. 2025 Hz for a zero data bit and 2225Hz for a one" data bit. Both the transmitted and received signals willbe passed on line 18 from junction 13 to a band separation filter 19which will remove the trans-.

mitted frequency band including the 1025 Hz and 1225 Hz signals and willpass the receiving band signals of 2025 Hz and 2225 Hz to a frequencydiscriminator 21. The discriminator 21 will respond to the receivedsignals to put a corresponding data signal on output line 22.

A time delay filter which can be used in the band elimination filter 19of FIG. 1 is shown in FIGS. 2 and 2A. Here an input signal on a lead 18corresponding to lead 18, FIG. 1, is applied to one side of a mixer 25and also to a delay line 26. Delay line 26 has a delay equal to one-halfcycle of the fundamental frequency which is to be filtered and has itsoutput connected to the other side of mixer 25. When the two signalsapplied to the mixer 25 are of equal effect, the frequency response ofthe circuit is as shown in FIG. 2A. It will be seen that the signal atthe fundamental frequency is cut out completely as is every odd harmonicof that frequency. However, frequencies near even harmonics of thefundamental are not appreciably affected and if two frequencies asindicated by the dotted lines 27 are chosen for data transmission, theywill pass through the filter without attenuation and can be used for thereceived data signal in a transmission system.

SPECIFIC EMBODIMENT OF THE INVENTION FIG. 3 illustrates how applicantuses the filter of FIG. 2 in a system as in FIG. 1. Here the delayelement 26 and mixer 25 form the band separation filter 19. However, thefilter of FIG. 2 has a very narrow notch frequency with steep sides andcannot be set to provide satisfactory attenuation for both of thetransmit frequencies. The delay element 26 is therefore adjusted to havea time delay equal to one-half of a cycle of the slower speed transmitsignal, i.e. 1070 Hz and is provided with a tapped point 27 at a delayequal to onehalf of a cycle of the higher speed transmit signal, i.e.1270 Hz. A switch 28 is provided to connect either the output lead 29 ofthe time delay 26 or the tapped lead 27 to the upper input to mixer 25so that the filter may be set to eliminate either the 1070 Hz or the1270 Hz frequencies. Switch 28 is controlled by the data signal on thetransmit data line so that it will be set to cause elimination of thefrequency being transmitted by the FSK transmitter 11 at any time. Thus,except for the short, part cycle interval immediately after a changeoverof switch 28, the filter 19 will be effective to remove substantiallyall of the signals being transmitted on the communications line 14 fromthe input to the frequency discriminator 21 which is therefore free toact on the received signal to decode its data content withoutinterference from the relatively stronger transmitted signal. a

FIG. 4 shows a digitally operating embodiment of the invention whichdoes not require precision delay lines or reactive components but ratheruses digital type onoff circuitry. This digital embodiment will bedriven by an oscillator circuit 31 operating at a frequency which isapproximately a high integral multiple of each of the nominal transmitfrequencies, e.g. 321.0 KHz which is 300 times the i070 Hz and 252 timesthe 1270 Hz signal frequencies to within a fraction of a percent. The

pscillator output 32 is divided by 2 in divider 33 to provide a basicclock output on line 34.

The FSK transmitter of this embodiment comprises a conventionalseven-bit wide counter 37 driven from clock output 34 and provided withtwo AND circuits 38 and 39. AND 38 is connected to the counter 37 and tothe data input lead 10 to give an output signal to an OR circuit 40 whenthe counter 37 reaches a count of 63, i.e. one-fourth of the 252multiple and data lead 10 has a data signal thereon. The other AND isconnected to counter 37 to give an output signal to OR 40 while thecounter 37 stands at a count-of 75, i.e. one-fourth of the 300 multiple.Each output of OR 40 on a line 41 switches a flip-flop 42 whose outputis thus a square wave at a frequency corresponding to the signal levelthen present on the data input line 10. The square wave output fromflip-flop 42 is passed to a line driver 43 which will drive thecommunications line 14. Line driver 43 comprises an input load resistor44 and an output resistor 45 with an operational amplifier 46 betweenthem. A feedback circuit comprising a resistor 48 and a capacitor 49 inparallel between the input and output of amplifier 46 will convert thesquare wave input from flip-flop 42 to a triangular shaped output signalwhich will be acceptable for transmission over the line 14. Since thetransmitted output signal contains only the fundamental and its oddharmonics, it is suitable for removal from the receiver input by thefilter circuit 19 as is indicated in FIG. 2A. The counter 37 will bereset by means of a latch circuit at the next transition of the clocksignal line 34 to a low level. As shown, an invert circuit 50 passes theclock signal as an inverted clock to its output line 51 which is aninput of a first NOR circuit 52. A second NOR circuit 54 has its outputconnected as the other input to NOR 52 and the output 55 of NOR 52 isboth the reset input to counter 37 and an input of NOR 54. The otherinput to NOR 54 is the output line 41 of OR circuit 40. The continuouspulsing ofline 51 will usually hold NOR 52 conductive and its output 55at a low level. Both inputs to NOR 54 are thus normally down and itsoutput will be up to maintain NOR 52 conductive. When OR 40 isenergized, its output line 41 will switch the conductive states of NORs52 and 54 to put a signal on lead 55 and reset counter 37. The NOR's 52and 54 will be switched back as soon as line 51 is pulsed at the nextdown phase of the clock cycle.

The receiver filter to remove the transmit signal comprises a deltamodulator 60 controlled by communications line 14 and pulsed by theclock signal on line 34. These delta modulators are well known devicesand provide on the output 61 a pulsed output signal representative ofthe rate of change of the applied input signal. Conventionally, thiswill be alternate pulses and spaces for an unchanging input, a higherproportion of pulses for an increasing input signal and a lesserproportion of pulses for a decreasing input signal. The delta modulatedoutput on line 61 is stored in a shift register having a number ofstorage positions equal to the reading of counter 37 for which AND 39will give an output and having an output 81 at the counter positioncorresponding to the reading of counter. 37 for which AND 38 will givean output signal. As in the embodiment of FIG. 3, a switch 28 controlledby the data signal on line 10 will connect either the output of the laststage of shift register 80 or the tapped output on' line 81 to the mixer25. The switch 28 comprises an AND circuit 82 having as inputs thetapped output on line 81 and the signal on line 10 to pass the deltamodulated signal when line 10 has a data bit thereon, an inverter 83 toinvert the data signal from line 10, an AND circuit 84 controlled byinverter 83 to pass the delta modulated signal from-the last stage ofshift register 80 and an OR circuit 85 to combine the outputs of AND's82 and 84 to an output line 86. The output signal on line 86 willtherefore be the delta modulated signal from modulator 60 with a delayequal to one-half cycle of the carrier then being transmitted, and thissignal on line 86 will be mixed with that on line 61 by the mixer 25.This mixer 25 is the same configuration as switch 28 with two ANDcircuits 90 and 91, an invert circuit 92 and an OR circuit 93. [t iscontrolled by the double clock speed line 32 to alternately connectlines 86 and 61 to an output line 95 whose signal will therefore be adelta modulated filtered signal corresponding to the signal beingreceived on line 14.

The counter 96 and the discriminator 97 are not a part of the inventivefeature but are included to complete a disclosure of the system. Counter96 is a non-overrunning counter and timed by the double clock signal online 32. It is controlled by the filtered signal on line 95. At eachpulse on line 32, counter 96 will be incremented or decremented in adirection controlled by the signal on line 95, Le. up if the signal ispresent and down if the signal is not present. The state of the highestorder bit of counter 96 is substantially the signal received on line 14and this signal is processed in discriminator 97 to generate thereceived data signal on output line 22.

It will be obvious that at the other end of the communication line, thetransmit and receive frequencies are interchanged and that it is thehigher frequencies which are to be filtered out of the signal on theline to allow receipt of the data from the other end. The frequencychange which is to be made in the clock 31 and the circuit changes inthe readout AND circuits 38, 39 of counter 37 together withcorresponding changes in the shift register 80 to enable filtering outof the transmit frequencies at the other end of the line will be obviousfrom the above description of the functions of these elements,

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in details may be madetherein without departing from the spirit and scope of the invention asset out in the following claims.

What is claimed is: 1. ln a full duplex data transmission system havinga single signal carrying circuit between at least two separated stationsand wherein each station includes both a data transmitter to impress onsaid circuit data signals represented by discrete frequencies within onefrequency band and a data receiver to translate data signals representedby discrete frequencies within another frequency band in said circuit;

the feature comprising a filter for eliminating said discretefrequencies within said transmission frequency band from the input tosaid receiver;

said filter including an adjustable signal delaying element to receivethe signals in said circuit;

switching means controlled by the data signals in said transmitter toset the delay of said delaying element in accordance with the discretefrequency being transmitted; and

a signal mixer to combine the output of said delaying element with thesignals then in said carrying circuit to supply to said receiver onlythe circuit data signals which are within said other frequency band.

2. A filter for a data transmission system as set out in claim 1 and inwhich said delay element comprises:

a shift register having a plurality of positions;

a clock controlling the discrete frequencies of said.

transmitter and shifting said shift register, the

transit time of a signal through said shift register being equal to anodd number of half cycles of the lowest frequency of said transmitter;

one or more connections to said shift register at positions where thetransit time is equal to an odd number of half cycles of other transmitfrequencies of said transmitter, said switching means selecting forconnection to said mixer, the shift register position corresponding tothe frequency being transmitted by said transmitter.

3. A filter as set out in claim 1 in which the signal on said signalcarrying circuit is delta modulated to generate a series of datarepresenting pulses;

a clock having a frequency integrally related to all of said discretetransmission frequencies and controlling said delta modulator;

a plural order shift register receiving the data pulses from said deltamodulator and shifted by the output of said clock;

' a connection to an intermediate position of said shift register, saidswitching means connecting the last or said intermediate position ofsaid shift register to an output line; and

a double clock speed line controlling said mixer to alternately selectthe output of said delta modulator or the switched output of said shiftregister to said receiverinput.

data transmission system operable m a full duplex mode over a singletransmission circuit between two or more stations, each stationcomprising a transmitter connected to said circuit and a receiverconnected to said circuit through a filter to isolate said receiver fromthe data signals put on said circuit by the transmitter at said station;

each station having a frequency controlling clock with a fundamentalfrequency output and a double fundamental frequency output;

said transmitter of a station comprising a counter driven by saidfundamental frequency output and providing an output signal at apreselected count therein and also a selectable output signal at alesser preselected count therein;

a data input line to control said selectable output signal;

counter reset means responsive to any output signal to reset saidcounter;

a flip-flop circuit connected to change state at each output signal fromsaid counter and to provide at its output a square wave signal at one oranother transmit signal frequency;

a line driver between said flip-flop and said transmission circuit todrive said transmission circuit with a triangular shaped wave having acorresponding frequency;

said receiver of a station being connected to said transmission circuitby a delta modulator controlled by said fundamental clock output toproduce pulses representing the total signal on said transmissioncircuit;

a shift register to store the pulse output of said delta modulator andshifted by said fundamental clock output, said shift register having anumber of storage positions equal to said preselected count and havingan output tap at a storage position equal to said lesser predeterminedcount;

a switch controlled by said data input line to connect either the laststorage position of said shift register or said output tap of said shiftregister to its output line;

a mixer circuit controlled by said double fundamental frequency outputto alternately connect the output of said switch and the output of saiddelta modulator to its receiver input;

a counter driven by said mixer circuit to convert the output of saidmixer circuit to a data representing signal; and

a discriminator to receive the output of said mixer and to convert saiddata representing signal to the data represented thereby.

1. In a full duplex data transmission system having a single signalcarrying circuit between at least two separated stations and whereineach station includes both a data transmitter to impress on said circuitdata signals represented by discrete frequencies within one frequencyband and a data receiver to translate data signals represented bydiscrete frequencies within another frequency band in said circuit; thefeature comprising a filter for eliminating said discrete frequencieswithin said transmission frequency band from the input to said reCeiver;said filter including an adjustable signal delaying element to receivethe signals in said circuit; switching means controlled by the datasignals in said transmitter to set the delay of said delaying element inaccordance with the discrete frequency being transmitted; and a signalmixer to combine the output of said delaying element with the signalsthen in said carrying circuit to supply to said receiver only thecircuit data signals which are within said other frequency band.
 1. In afull duplex data transmission system having a single signal carryingcircuit between at least two separated stations and wherein each stationincludes both a data transmitter to impress on said circuit data signalsrepresented by discrete frequencies within one frequency band and a datareceiver to translate data signals represented by discrete frequencieswithin another frequency band in said circuit; the feature comprising afilter for eliminating said discrete frequencies within saidtransmission frequency band from the input to said reCeiver; said filterincluding an adjustable signal delaying element to receive the signalsin said circuit; switching means controlled by the data signals in saidtransmitter to set the delay of said delaying element in accordance withthe discrete frequency being transmitted; and a signal mixer to combinethe output of said delaying element with the signals then in saidcarrying circuit to supply to said receiver only the circuit datasignals which are within said other frequency band.
 2. A filter for adata transmission system as set out in claim 1 and in which said delayelement comprises: a shift register having a plurality of positions; aclock controlling the discrete frequencies of said transmitter andshifting said shift register, the transit time of a signal through saidshift register being equal to an odd number of half cycles of the lowestfrequency of said transmitter; one or more connections to said shiftregister at positions where the transit time is equal to an odd numberof half cycles of other transmit frequencies of said transmitter, saidswitching means selecting for connection to said mixer, the shiftregister position corresponding to the frequency being transmitted bysaid transmitter.
 3. A filter as set out in claim 1 in which the signalon said signal carrying circuit is delta modulated to generate a seriesof data representing pulses; a clock having a frequency integrallyrelated to all of said discrete transmission frequencies and controllingsaid delta modulator; a plural order shift register receiving the datapulses from said delta modulator and shifted by the output of saidclock; a connection to an intermediate position of said shift register,said switching means connecting the last or said intermediate positionof said shift register to an output line; and a double clock speed linecontrolling said mixer to alternately select the output of said deltamodulator or the switched output of said shift register to said receiverinput.